Digital data processor



SPt- 20, 1966 R. s. SHARP ETAL.

DIGITAL DATA PROCESSOR 14 Sheets-Sheet. l

Original Filed Jan. 5. 1961 Sem. 20, 196s R. s. SHARP ETA'. 3,274,558

DIGITAL DATA PROCESSOR Original Filed Jan. 5. 1961 14 Sheets-Sheet.

Sept 20, 1966 R. s. SHARP ETAI. 3,274,558

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Sept. 20, 1966 R. s. SHARP ETAL 3,274,558

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DIGITAL DATA PROCESSOR Original Filed Jan. 5. 1961 14 Sheets-Sheet J 14 Sheets-Sheet l0 Original Filed Jan. 5. 1961 Mmm?? m//f- 42 0MM/mw wor@ Sept. 20, 1966 R. s. SHARP ETAL DIGITAL DATA PROCESSOR 14 Sheets-Sheet. 1 1

Original Filed Jan. .'5. 1961 /fffW/.f//f//f//f//f//A/ 000090000000001//f/f////l /fliOO miU/J/w/5f565555000005 6:50-00:0000 m 00000000008555000000 07 70|0/-f000 W` 00044402200777703330-f0-6600-6,900 m 00000000000000000000,00-0.0--00s0000 m 00000300020002000020-0.0122120-2200. mfmzaa/f/f//f/////00000o-00:05:0515050 #@00222?222?222Z//////|//--/0--00J0650 MO//f/f/f/////00000IOIDMIOO MOO//f/f//f/f/f/l-/f/////l// *hmmm/2330250025502333025,27:54-0/:5522 Im000000/000/.000/0000/.0/:0/t0i10/00 Mwm|no0000000000000//000010020/,0020//0 WMMMWOZ/57665433#$9998766:35:99153I999H m|wf4|il56i||l78siil9m4iti5 67:60.167159MH Sept. 20, 1966 R. s. SHARP ETAL DIGITAL DATA PROCESSOR Original Filed Jan. 5. 1961 SN10LS-Sheet l 14 .31mm @s She-U. 15

Sept. 20, 1966 R. s. SHARP E'I'AL.

DIGITAL DATA PROCESSOR Original Filed Jan,I 3. l

Sept. 20, 1966 R. s. SHARP ETAL.

DIGITAL DATA PROCESSOR 14 Sheets-Sheet 14 Uriginal Filed Jan. I5. 1961 Unite States Patent O 3,274,558 DIGITAL DATA PROCFSSR Richard Stanton Sharp, Sierra Madre, Calif., Dan Allan Neilson, North Palm Beach, Fla., and James Russell Bennett, Glendora. Calif., assignors to Burroughs Corporation, Detroit, Mich., :l corporation of Michigan Continuation of application Ser. No. 80,171, Jan. 3, 1961. This application Oct. 19, 1965, Ser. No. 505,123 33 Claims. (Cl. S40-172.5)

This invention relates to computing machines and, more particularly, to digital data processors.

This case is a continuation of a previously filed application Serial No. 80,171, filed January 3, 1961 and now abandoned by the same inventors as this patent application.

Data processors are generally arranged for processing data at a relatively high rate of speed. The data processors have a single memory unit for storing commands and operands to be processed. To allow as short a computing or processing time as possible, data processors have been arranged so that one of the steps of the operation is bringing a full command out of a memory unit for storage in some type o1 intermediate command register. The command of a three-address data processor has two addresses of locations in the memory unit where two operands to be processed are stored, the address of a location in the memory unit where the result of the processing of the operands is to be stored and an order denoting the arithmetic operation to be performed on the operands. The next step of operation is to address the memory unit with the operand addresses and shift the operands out of the memory and store them in other intermediate or operand registers in accordance with the fetched command. The operands are then processed and finally the result is stored in the memory unit.

With such an arrangement there is a great duplication ol' storage apparatus. For example, four intermediate storage registers are needed for storing the three addresses and the order when actually only one of the addresses in a command is used for addressing the memory unit at any one point in time. Also many times only portions of operands are processed at a time and yet, the full operands nre stored in the operand registers. Since only part of cach operand is processed at a time, the rest of the operand could just as well be left in the memory unit until actually used. lt should be noted that the memory unit in such an arrangement is addressed for reading and storing information only about ten percent of the total time. Thus, the memory unit is not used very efficiently.

Many banking systems use punched cards for storing information. This means that most of the input and output devices for a data processor in a banking system will be card readers, card punches and the like. Such inputoutput devices are relatively slow, compared with the higher speed electronic data processing machines mentioned hereinabove, causing processors to waste time waiting for the lower speed input and output devices to read processed data from the data processor and read information from punched cards, etc., for input to the data processor.

Data processors also are known which process variable length operand or data signals. Generally, such machines require special identification bits in the memory unit accompanying each variable length operand to designate length. Then when the operands are processed they are generally converted to fixed word length operands.

The present invention provides an improved data processor wherein the number of intermediate storage registers and the lengths thereof are kept to a minimum by shifting only parts of two operands out of the memory unit, processing those parts of the operands and storing Mice the result in the memory unit before other parts of the operands are shifted out for processing. Also each operand is processed as a true variable length operand without the necessity of converting it to a fixed-length word. This is accomplished by handling all operands in characters composed of a tixed number of binary bits and by the use of special Field length characters in each command to designate the number of characters in, or the length of, each operand. By handling variable field length operands in fixed length characters the data processor of this invention actually processes two fixed length nombers at a time, thereby providing a tremendous savings in registers and gating circuits, which otherwise would be needed for converting the full variable length operands to a fixed length word.

The present invention also provides an improved data processor which allows the execution of a command to be interrupted during the processing of each character of two operands. This allows one or more butler units to be made a part of the main memory for use in storing new data characters from input units and shifting out protessed data to output units. By this arrangement reading and writing in the butler unit may be done using substantially the same address registers and, in a core memory unit7 the same core driving circuits for the buier unit as used for the memory unit. Also, by interrupting the processing for reading a new data character at n time from peripheral punched card readers, the peripheral card units may operate independently of the processor at their own speed, and yet allow each character of data to he read from the peripheral unit as presented therein; and stored in the special butler unit. The data characters in the buffer unit may then be transferred to main memory under control of a separate data processing command. Thus, a data processor is provided whose actual processing speed is slower than conventional data processing machines. However, by the use of the speciai interrupt feature, the special bullet' unit and operation by characters, the speed of the data processor is completely mmpatible with peripheral character oriented data units` and due to increased speed provided by the battering units, the data processor is still faster than the fastest card rend and card punch units available. This arrangement allows the cost of a data processor to be reduced to approximately one-half that of comparable prior art data processors, due to the savings in register circuits and buffer core driving circuits.

Briefly, a specific example ofthe present invention provides a character oriented data processor having a storage unit for storing binary coded digital operands and commands. The operands are composed of a variable number of characters, each of which is composed of n iixed number of binary bits. The commands are also composed of characters, and the characters of the commands along with :the characters of the operands are stored in addressable storage locations of the storage unit. Each command contains the beginning addresses of a memory field where characters of two operands are stored, the beginning address of a memory field where characters of the result of the processing of the operands are to be stored, an order character for specifying the type of operation to be performed on lthe operands and two field length character for specifying the eld length of each operand specified in the command. A command address register and a command character register provide the command address signals to the storage unit. The command register addresses the particular command being used and the command character register addresses the characters within the particular command in a prescribed order. A memory address register addresses operands in the storage unit causing the operands to be shifted out of the storage unit a character at a time. A processing unit is coupled to the storage unit. The processing unit is arranged for processing operands a character at a time and for adding field length characters to the beginning operand addresses as the addresses are shifted out of the storage unit so as to form addresses of the characters within each operand being processed. Two field length registers are provided for storing the two field length characters and are arranged for decreasing the magnitude of the field length characters in between processing of characters of operands so that when they are added to the beginning addresses of operands the resulting address is that of the next character to be processed. The addresses determined by the processing unit are stored in the memory address system.

A better understanding of the invention may be obtained with reference to the following detailed description of the drawingsI of which:

FIG. 1 is a general block diagram of a data processing system embodying the present invention;

FIG. 2 is a detailed block diagram of the data processing system shown in FIG. 1;

FIGS. 3A through 3M are detailed schematic diagrams of thc gating circuits shown in FIG. 2;

FIG. 4 is a diagram illustrating the word structure of the commands used in the data processing system of FIG. 2 and an example of a typical command word;

FIG. 5 is an example showing the contents of the memory locations needed for executing the exemplary command shown in FIG. 4;

PlG. 6 is a timing diagram illustrating the states of the flip-flop circuits and register circuits in the data processor of FIG. 2 when executing the exemplary command, step by step, of FIG. 4 on the operands of FIG. 5;

HG. 7 is an exemplary timing diagram for the operation of the flip-flop circuits and registers in the data processor of FIG. 2 when new data characters are stored in the storage means;

lilGS. 5A and 8B, taken vtogether as shown in FIG. 8, comprise .t liow chart illustrating the sequence of operation of thc data processor of FIG. 2;

VfG. J is a partial block diagram and partial functional diagram showing an example of data characters being shifted out from the source of data signals and stored in the holler unit of the storage means;

HG. ttl is a diagram illustrating the sequence of the reading and writing pulses for the memory unit and its asrriciated buffer unit, and;

HG. Il is a diagram showing the representative states of operation of the register consisting of the flip-flops F1 and F2 corresponding to their binary digit representations.

Referring now to FIG. 1, a general block diagram of the adding .system portion of a data processor is shown having a storage means 10 for storing commands and operands, composed ot characters which are to he processed, edited and finally shifted out to peripheral output units 1l. The storage means 10 contains individually addressable storage locations each of which is arranged for storing a single character of information. One or more of these .storage locations will be referred to as operand and result fields for storing the variable length operands and the results of the processing of the operands. Each character of information is composed of a fixed number of binary coded digital signals.

The storage means 10 receives address signals from a command address register 12, a command character register 14 and a memory address register 16. The address signals developed by the command address register 12 specify a group of storage locations in the storage unit 10 which contain the particular command to he executed. The command character register 14 develops address signals for specifying the locations of particular characters within the specified command.

To be explained in more detail hereinafter, for the present it should be noted that each command has 12 characters. Referring to FIG. 4, it will be seen that one of the characters specifies the order or type of operation to be performed on the operands, two of the characters are field length characters and specify the length of the field of the two operands, six of the characters specify the beginning addresses of two operands and three of the characters specify the beginning address of the field where the characters of the result of the process on the operands are to be stored.

The first character of the command to be addressed by the command character register 14 is the order character which is shifted out of the storage means 10 and stored in an order register 18 (indicated by dashed lines) in a timing unit 20. Next, the command character register 14 addresses the storage locations storing the two field length characters which will be called the A and E field length characters, Af and Bf. The A and B field length characters are then individually shifted out of the storage means 10 and into the input circuit of a processing unit 22. The processing unit 22 has an adder circuit 23 which decreases the magnitude of the A and B field length characters by one, as shifted out of the storage ymeans l0. The moditied field length characters are then stored in A and B field length registers 28 and 26 (indicated by dashed lines) in the timing unit 20.

To be explained in detail, the magnitude of the addresses of the storage locations in the storage means 10 increases in magnitude, while the order of the characters of the operands stored in those storage locations decreases. Thus, the beginning address of an operand field is the address of the storage location of the most significant character of the operand. Thus, when the length of an operand field is decreased by one and added to the beginning address of the operand field, the address of the least significant character of: the operand is obtained.

The operation at this point is dependent on the type of order stored in the order register 18. Assume that the order character stored in the order register 1B specifies that the two operands identified by the beginning operand addresses are to he added together with the magnitude of the A and B field length characters decreased by one and the result stored in the field length registers 26 and 28, the command character register 14 addresses the storage locations containing the three characters of the beginning address of the B operand. The three characters of the beginning address of the B operand are shifted out of the storage means 1U and into the processing unit 22. The processing unit 22 adds the modified B field length character in the field length register 26 and the resultant B operand address is stored into the memory address register 16. The memory address register 16 now contains the address of the least significant character of the B operand. The storage means 1i) is now addressed by the memory address register 16 and the least significant character of the B operand is now shifted out of the storage means 1t) and stored in the B operand register 30 (indicated by dashed lines) in the processing unit 22.

The command character register 14 now addresses the storage locations containing the three characters of the beginning address of an A operand. The storage means 1I) now shifts out the three characters of the beginning address of the A operand. The processing unit 22 adds the modified A field length character to the beginning address of the A operand and the result is stored in the memory address register 16. Similar to that for the B operand the storage means 10 is again addressed by the command character register 14 and the least significant character of the A operand is shifted out of the storage means 1t) and stored into an A operand register 32.

With the A and B operands stored in the operand registers 30 and 32 of the processing unit 22, the command character register 14 now addresses the three characters of the beginning address ofthe result field. The three characters of the result address are shifted out of thc storage means 10 and into the processing unit 22. The processing unit 22 modifies the beginning address of the result field by adding to it the larger of the modified A and B field length characters. stored in the field length registers 26 and 2S. The modified beginning address of the result field is the address of the result field where the least significant character of the result will be stored. The modified beginning address of the result field is then stored in the memory address register 16.

The processing unit 22 now combines the operands stored in the A and B registers 30 and 32 and a partial sum character representing the sum is applied at the input of the storage means 1l) by the processing unit 22. This is the least signicant partial sum character. The memory address register 16 then addresses the storage means 10 and the least significant partial sum character is stored in the addressed storage location of the storage means 10. Also, the modified field length characters in the field length registers 26 and 28 are decreased by one.

With the result of the processing of the first character of the two operands stored, the storage means 10 is again addressed by the command character register 14 and shifts out the beginning address of the B operand. The processing unit 22 now adds the new modified B fleld length character, stored in the register 26, to the beginning address of the B operand and the result is stored again in the memory address register 16. The modified addi-ess stored iii the memory address register 16 is now the address of the next to the least significant character of the B operand. The storage means 1t) is again addressed by the memory address register 16, and the next to the least significant character of the B operand is shifted out and stored in the processing unit 22.

Similarly. the beginning address of the A operand is again shifted out, modified and stored in the memory address register 16. Subsequently, the contents of the memory address register 16 is used to address the storage nicaiis 1t) arid the next to the least significant character of the A operand is shifted out and stored in the A operand register 32. The command character register 14 again addresses the memory locations containing the beginning address of the result field. This result address is shifted out, modified by the larger of the two modified field length characters in the registers 26 and 28 and the modified result address again is stored in the memory address register 16. The modilied result address is now the address of the result field for storing the next to the least significant surn character. The two operand characters in the processing unit 22 are now combined similar to the first characters of the. operands and a character representing the sum stored into the storage means 10. The magnitude of the two modified field length characters stored in the registers 26 and 28 are again decreased by one.

This sequence of operation is repeated until the contents of both the field length registers 26 and 28 have been counted down to an initial state. At this point thc two operands are completely combined and the surn stored in the result field of the storage means 1G. The command address register 12 then addresses the next command and the operation specified by the new order is executed.

1t should be noted that a carry from the addition of two operand characters is combined with the addition of the next most significant characters. To this end, a flip flop circuit (flip-flop Cal shown in FIG. 2) is provided in the adder circuit 23 for providing an indication of a carry from a previous addition. A source of data signals 34 is also connected to the storage means 10 for supplying new data signals or characters of digital signal information. The source of data signals 34 may be a punched card reader or the like which repeatedly supplies data signals or characters to the storage means 10 a character at a time at a speed determined by its internal operating speed. To be explained in detail in the following description, the above described sequence of operation of the processor itself is interrupted during the processing of each character of the operands so that the storage means 10 may read and store the character of information presented by the source of data signals 34, before the character of data is lost.

Having the general operation of the data processor of FIG. 1 in mind, a brief description of terminology to be used in the following detailed description of figures will be given. Flipdlop circuits will be referred to by capital letters, followed by a number, i.e., T1, RI, ete. Each flip-flop circuit has two output circuits which will be referred to by the letter design-ation of the flip-flop followed by the number subscript of the flip-'flop To distinguish between output circuits, one of the output designations will have a prime affixed; thus, Tl, T1', R2, R2', etc. Flip-flop circuits have two states of operation which will be referred to as the true and false states. or by saying the flipd'lop circuits represent a digit l and digit t), respectively. When a flip-flop circuit represents a digit 0, the primed output circuit is at a high potential level, and the unprinied at a low potential level. lf the flip-flop circuit represents a digit 1, the primed Jatstiitii circuit is at a low potential level and the unprimcd ouiput circuit is at a high potential level. In the following discussion flip-op circuits will be said to be set" when triggered to represent a digit l and reset" when triggered to represent a digit O.

Gating circuits are used to control the triggering of flip-flop circuits into their states ot operation. In the following description, each of the fiipdlop circuits, and register circuits as well, will be understood to he ti iggcied or set to different states only at `the occurrencev of a clock pulse signal, unless otherwise stated, whenever the cor responding input control, from, for example, a gating circuit, is at a high potential level.

With the general description of FlG. l in mind, a `tietailed description will be given of the data processor systern of FIG. t shown iii detail in FlG. 2. The timing unit 20 contains a signal generator 36. The signal generator' 36 contains five timing flipdlopp: indicated by the symbols Tl, T2, Fl, F2 and R2 (indicated by dashed lines). Also priovidcd is `a clock pulse generator 38. The clock pulse generator 38 has an output circuit Cl at which rectangular recurring clock pulse signals are provided to each of the flip-flop circuits, the register circuits andthe storage means 10 in the data processor of FIG. 2. The signal generator 36 also contains gating circuits indicated by the general symbol 4G, The gating circuits 40 provide the gating or control signals to each of the flip-flop circuits, register circuits, the processing unit 22 and the storage means 1t) in `the data processor of FIG. 2, for controlling the states of operation thereof. Detailed circuit diagrams of' tlic gating circuits 40 are shown in FIGS. 3A through 3M.

Before describing the gating circuits 40 in detail, a brief explanation will now be given of the word structure of the commands and the operands. The storage means l() contains a memory unit 42 which is a coincident cnrrent magnetic core memoryr unit. The memory unit 42 has a plurality of separately addressable memory locations, eacli for storing a character of binary coded decimal digital information. For purposes of illustration, it is'iassumed that each character of information has four binary coded decimal bits and each of the memory locations in the memory unit 42 contain four core units for storing the four binary bits representative of each decimal character. Refer now to FIG. 4, where an illustration of the word structure of the command is shown. At the `top of FIG. 4 a command is shown to consist of an order character, A and B eld length characters, three characters for specifying tlie beginning address of an A operand, three characters for specifying the beginning address of a B operand and three characters for specifying the beginning address where the result of the process of the operands is to be stored. The lower pontion of FIG. 4 is an example showing a typical command word stored in the memory unit 42. 111e characters of the command word in the memory unit 42 are aligned with the illustration of che command structure shown at the top oi FIG. 4. At the left; an order character 1 is shown. An order character 1 specities that an addition is to be performed on `the two operands specied by the command. The beginning address of the A operand is 200. The A operand is three characters long. The beginning address of thc B operand is 203 and the B operand is two characters long. The beginning address of the result `held is 205. To be explained in the following discussion, the processor of FIG. 2 takes the longer of the two field length characters, which in this case would `be the A tield length character three, and uses this character as the length of the result field.

FIG. 5 shows the contents of the memory locations specified by the A and B operands in FIG. 4 iand the resuit held. The beginning address of the A operand is 200, and the length of `the A operand is three characters, therefore, the A operand is the number 178. The begnning address of the B operand is 203 and the length of the B operand is two characters, therefore, the B operand is the number 65. The result field will then include the beginning address 205 tand the addresses 206 and 207.

The command character register 14 receives set control signals for controlling its states of operation, from the output of the gating circuits 40. The command character register 14 develops coded output signals which are both address signals for the storage means 10 and timing signals for control of the gating circuits 40.

FIG. 3A shows the command character register 14 with its associated input circuits, which are designated through ll and 15, for receiving set signals `for setting the register into various states of operation.

Gating circuits (not shown) are coupled between the input lines, bearing the set signals and tlip-tlop circuits [not shown), and are responsive to low potential set signals for setting the ilip-llop circuits into corresponding representative states of operation. The command character register ialso has thirteen output lines designated rtl through r11 and r15, which correspond to the state of operation 0 through l1 and l5, respectively. Gating circuits (not shown) are also coupled between the ipiiop circuits and the output circuits ttor developing a high potential signal on an output line whenever the command character register is in the corresponding state of operation.

Five inhibit gates 44 are connected to the output circuits rO, r5, f8, r11 and rl5 of the command character register 14. The inhibit gates 44 each have an input control circuit connected to the R2 output circuit of the reader access timing flip-flop R2. Whenever the reader access tlipd'lop R2 represents a binary digit l, or is in a true state, a high potential signal is developed at the control input of the inhibit gates 44, causing the inhibit gates 44 to block any high potential input signal and cause `a low potential output signal regardless of the input signal thereto.

The command character register 14 has its thirteen input lines for receiving a set signal connected to a command character register' gating circuit 45. The command character register gating circuit 45 has input circuits conneeted to `the output circuits of the command character register 14, the iip-op circuits F1 and F2 and the output circuits designated Af=15, AlS, Br=l and 1317415 of the A and B field length registers 28 and 26 (see FIG. 3l). The output circuits rlS, r2, r0, r4, f5, r7, r8, r10 and r11 are connected to the input circuits of the command character register 14 for setting the register into the states D, l, 2, 3, 4, 6, 7, 9 and 10, respectively. The input circuit for setting the command character register 14 into state 5 is connected to an output circuit of an or gating circuit 47, which has two input circuits. The two input circuits of the or" gating circuit 47 are connected to output circuits of two and gating circuits 46 and 48. The and gating circuit 46 has tive input circuits. Three input circuits of the and gating circuit 46 are connected to the output circuit r9 of the command character register 14 and the F1' and F2 output circuits of the tliptlop circuits Fl and F2. The other two input circuits of the "and" gating circuit 46 are connected to the 81:15 and the AlS output circuits of the B and A iield length registers 26 and 28, respectively.

Referring to FIG. 3l, the B and A field length registers 26 and 28, respectively, are shown in dashed lines. The A tield length register 28 has output circuits Af=15 and AelS. Whenever the A field length register is storing a number equal to 1S, the output circuit Af=l5 will be at a high potential level; at all other times it is at a low potential. Whenever the A leld length register 28 is storing a number which does not equal l5, then the output circuit AFIS will be at a high potential level; at all other times the AQIS output circuit is at a low potential. Similarly, the B field length register 26 has output circuits Bf=15 and 89H5, at which high potential signals are developed when a number stored therein is equal to l5 and is not equal to l5, respectively.

Referring again to FIG. 3A, the and gating circuit 48 has three input circuits. One input circuit is connected to the r6 output of the command character register 14 and the other two input circuits are connected to the Fl and the AIS output circuits of the Fl flip-flop and the A tielcl length register 28, respectively. The input circuit for setting the command character register 14 to state 5 is connected to the input circuit of an or" gating circuit 58, which has two input circuits. The two input circuits of the or gating circuit 53 are connected to the r1 output circuit of the command character register 14 and the out- -put circuit of an "an gating circuit 60. The "and" gating circuit 60 has four input circuits. Two of the input circuits are connected to the output circuits r9 and H5115 of the registers 14 and 26, respectively, and the other two input circuits are connected to the output circuits Ft' and F2 of the F1 and F2 flip-flop circuits. The input circuit of the command character register 14, for setting it into state ll, is connected to an output circuit of an or" gating circuit 50. The or gating circuit 50 has its input circuits connected to the output circuits of anrl" gating circuits 52 and 54. The and" gating circuit 52 has two input circuits which are connected to the r3 output circuit of the command character register 14 and the F1 output circuit of the Hip-flop circuit F1. The and gating circuit 54 has three input circuits which are connected p to the r6 output circuit of the command character register 14, the Af: 15 output circuit of the A field length register 28 and the F, output circuit of the llip-ilop circuit F1.

The input circuit for setting the command character register 14 into state 15 is connected to an output circuit of an and gating circuit 56, which has five input circuits. The and gating circuit 56 has three of its input circuits connected to the output circuits r9, A1215 and B1+15 of the registers 14, 28 and 26, respectively. The other input circuits are connected to the output circuits F1' and F2 of the flip-Hop circuits Fl and F2. A start switch Swl (see FIG. 2) is connected between the command character register 14 and ground (0 volt potential). Whenever it is actuated it resets the command character register 14 to state 0, regardless of its present state.

Having the structure of the command character register gating circuit 4S in mind, a brief explanation will now be given of its operation with reference to FIGS. 8A and 8B. FIGS. 8A and 8B form a iiow chart which shows the sequence of operation of the processor of FIG. 2. At the beginning of each program step, the state ofthe command character register 14 is shown, which will give an indication of its sequence of operation in the following discussion. Whenever Swl is actuated, the following clock pulse signal will trigger the command character register 14 into slate t). With the command character register 14 in slitte 0, the following live clock pulse signals will trigger the command character register into states 2, l, 8, 7 und 6. When the command character register 14 is in state 6, the following clock pulse signal will trigger it into suite if the contents of the A eld length register 28 is not equal to l5, and it will be triggered into state 11 if the contents of the A field length register 28 is equal to 15. When the command character register 14 is in state 5, thc following tour clock pulse signals will trigger it into strilcs 4, 3, 1t and 9, respectively. With the command churucter register in state 9, the following clock pulse .signal will trigger it buck into state 5 if the contents of the A licld length register 28 is not equal to 15, the contens of the B field length register is equal to 15, and the flip-flop circuits F2 and F1 represent digits 1, l). If, however. the contcnts of the B field length register is not equal to l5 und the llip-flop circuits F2 and F1 represent digits 1, l), the following cock pulse will trigger the command character register 14 from state 9 to state 8. When both the` contents of the A eld length register 28 and the B field length register 26 are equal to 15 and the flip-flop circuits F2 and F1 represent digits 1, the following clock pulse signal will trigger the command character register from state 9 to state l5. With the command character register 14 in state l5, the following clock pulse signal will trigger thc command character register into state 0. it should he noted, however, that whenever the command character register 14 is in states U, 5, 8, ll `and 15, the ft'illuwing clock pulse signnl will not be effective to trigger it into the next statte of operation, if the reader access jlip-llop R2 represents a digit 1, since the inhibit gates 44 will inhibit the output signals of the command character register 14.

The :l5 output `circuit of the command character register td.- is connected to the count input circuit of the command ndd'css register l2. Whenever the command charnctciA register l is in slate 15, the following clock pulse muses the command address register 12 to count to its next itate oi operation. The command character register continues, from an inhibit stntc, counting up to a presclcclcd state where it counts back to the initial state of opcrution. The commi-.nil chnractcr register is also connected to the start switch SW1, which resets it `to an initial stilte of operation when actuated.

With the command character register gating circuit 45 ,in mind, the gisting circuit 62 for the tiip-tlop circuits Fl :intl l2 will now be described. The flip-flop circuits F1 und F2 have tour possible representative states of operation, as shown in FIG. tl. With reference to FIG. 1l, whenever both F1 und F2 ure false, they are said to he in stuur u. Also. whenever thc flip-flop circuits F2 and F1 repre :cnt digits 0, l, l, t) and l, l, respectively, the fliptlops F2 and Fl arc said to be in the representative states l, 2, and 3, respectively. The input circuit for setting the tlpwllop circuits F1 und F2 into a 0 representative state is connected to the output circuit of an "or" gating circuit 64. The or gating circuit 64 has two input circuits which are connected to the output circuits of and" gating circuits 66 und 68. The and gating cirucit 66 has its input circuits connected to the output circuit R1' of a flipllup circuit R1 (shown by clashed lines) in the source of tinta signals 34 and an output circuit BAP of a butler access gnting circuit 69 shown in FIG. 3D. The and" gating circuit (i8 hns three input circuits which are connected to the output circuit r3 of the command character f r 14 :ind the output circuits F1 and F2 of the flipllop circuits F1 and F2. The input circuit for setting the llip-flop circuits Fl` and F2 into a l representative state is connected to the output circuit of an or gating circuit 70. The or` gating circuit 70 has three input circuits rlich are connected to thc output circuits of "an gating circuits 72 und 74, and the r6 output circuit of the commund character register 14. The "and gating circuit 72 has three input circuits which are connected to the output circuit r3 of the command character register 14 and the output circuits F1' and F2' of the flip-flop circuits F1 und F2. The and" gating circuit 74 has two input circuits which are connected to the output circuit BAP of the butler access gating circuit 69 and the Rl output circuit of the flip-flop circuit R1. The input circuit of the Hipop Circuits F1 and F2 for setting it into a state 2 is connected to an output circuit of an or" gating circuit 76. The or gating circuit 76 has two input circuits which are connected to the output circuits of and" gating circuits 7S and 80. The "and gating circuit 78 has three input circuits. The three input circuits are connected to the output circuits R2 and F1 of the flip-flop circuits R2 and F1, and an Ma output circuit ot' the memory address regster 16. Referring to FIG. 2, the M8 output circuit of the memory address register 16 is the output; of a ip-op circuit M8 (indicated hy dashed lines) contained therein. The input circuit of the and" gating circuit 80 is connected to the r9 output circuit of the command character register 14 and the F1 and F2 output circuits of the Hip-Hop circuits Fl and F2. The input circuit for setting the flip-Hop circuits F1 and F2 lo state l is connected to an output circuit of :1n and" gating circuit 82 which has three input circuits. The three input circuiti'` are connected to the r9 output circuit of tht` command character register 14 and F1' and F2' output circuits of the flip-flop circuits F1 and F2. The flip-Hops F2 und F1 are also connected to the Hip-flops F1 and F2, for reselting them to a 0 representative state.

With the detailed description of the F1 and F2 gating circuit 62 in mind, :1 brief description of its operati-in will now be given. Referring again to the now dingrniu of FIGS. 8A and 8B, an indication of the comme ot operation of the timing tliplops F1 and F2 may he observed at the input to euch of the program steps shown. At the lower right hand corner of program steps 5, 1U, ll and 14, a note is made indicating that the butler access gating circuit 69 develops a high potential signal during those program steps. Therefore, if the render access flip-Hop R1. in the source of data signals 3d. represents a digit O the timing flip-ops F1 and F2 will hoth be reset during program steps 5, 1U, 11, and t4. During program step 7, the command character register 1t is in state 3 and the timing flip-flops Fl and F2 represent digits 1, 0. Therefore, the following clock pulse res-:its both the timing Hip-flops F1 and F2 to represent a digit (l. During program steps 4 and 6, the command character register 14 is in states 6 and 3, respectively. Therefore. the timing Hip-flops F1 and F2 will be set to represent digits l, tl, during program step 4 and during program step 6 if both the flip-flops Fi and F2 represent a digit 0. Also, the ip-tlop circuits Fl and F2 will be set to represent digits 1, O when the buffer access permitted signals are de velopcd during program steps 5, l0 and ll, if the reader access tlip-tlop R1, in the source of data .signals 34. represents a digit l. Referring to FIG. 2, a buffer unit 96 is provided. Whenever signals are to be written into cithcr the buffer unit 96 or the memory unit 42. the timing flip-flops F1 and F2 are triggered to represent digits 0, 1. Whenever signals are to be written into the butler unit 96, the ip-op circuits R2, M8 and F1 all represent a digit 1. This occurs during program step l2 and the following clock pulse triggers the timing tlip-liops F1 and F2 to represent the digits 0, 1. During the program step 10, signals are written into the memory unit 42. At this time, the command character register 14 is in state 9 and the timing Hip-flops F1 and F2 both represent u digit l, causing the following clock pulse to trigger the timing flipfiops F1 and F2 to represent digits 0, 1. During the program step 9 signals stored in the A and B operand registers 30 and 32 are added. It is only during program step 9 that the timing flip-ops F1 and F2 both represent a digit 1. Therefore, during program step 8 the command character register 14 is in state 9 :1nd the timing l l flip-hops F1 and F2 both represent a digit 0 and the following clock pulse triggers both the flip-flop circuits F1 and F2 to represent a digit 1.

With the command character gating circuits 45 and the F1 and F2 flip-Hop gating circuit 62 in mind, the gating circuits 79 and 81 for the timing ip-ops T1 and T2, respcetively, will now be explained with reference to FIG. 3C. To he explained, the timing Hip-flop T1, is used for controlling the set of the timing {lip-flop T2, and the fliptlop circuit T2 indicates the larger of the two field length characters. The T1 flip-flop gating circuit 81 is connected to thc T2 tlip-tiop circuit indicated by dashed lines). The set input circuit or the input which controls the setting of flip-flop T1 to represent a digit l is connected to the r2 output circuit of the command character register 14. The input circuit for resetting the timing ip-op T1, or resetting it to represent a digit 0. is connected to an output circuit of an and" gating circuit 84. The and gating circuit 84 has three input circuits which are connected to the output circuit r9 of the command character register 14 and the F2 and F1 output circuits of the ip-flop circuits Fl and F2. Thus, referring to FIGS. 8A and 8B, the timing flip-tlop T1 will be set during program step 2 after a new order is shifted out of the storage means 10 and will be reset during program step 9 when the command character register is in state 9 and both the ip-tlop circuits Fl and F2 represent a digit 1.

The timing flip-flop T2 has its set circuit connected to an output circuit of an and" gating circuit 86 of the T2 gating circuit 79. Before explaining the input circuits of the and" gating circuit 86, a brief explanation of output circuits from the processing unit 22 will be given. Referring to FIG. 2, the processing unit 22 has an adder circuit 88. The output circuit of the adder circuit 88 has a group ot sum lines 93 for developing signals which represent the result of its operation. Two output lines (il. and CL are provided for indicating any carry-out for the next character to be operated on. Whenever a high potential output signal is developed at thc output circuit CL, there is a carry-out to the next character to be proccsscd. Whenever the output circuit CL is at a high potential, it indicates that there is no carry-out. Referring again to FIG. 3C, the and gating circuit 86 has its four input circuits connected to the output circuit CL of the adder circuit 88, the output circuit r6 of the command character register .[4 and the F, and T1 output circuits of the Hip-flop circuits Fl and T1. The input circuit. ci the timing flip-flop T2, for resetting it, is connected to the rlS output circuit of the command character register. Thus, whenever a new order has been shifted out of the storage means 10 and the first characters of two operands are being processed, the timing flip-flop T1 is true, the flip-flop circuit F1 is true and the command character register 14 is in statte 6, the timing flip-flop T2 will be set if there is a carry-out signal from the adder circuit 88. The timing flip-flop T2 will then be reset during state l of the command character register 14. Both the flip-llops T1 and T2 are connected to the start switch SW1, and are reset whenever it is actuated.

Referring again to FIG. 2, the memory unit 42 of the storage means has its input circuits, for receiving address signals, coupled to the output circuits of the memory address register 16. the command address register 12 and the command character register 14. As mentioned, the memory unit 42 is a coincident current core unit and has gating circuits (not shown) for decoding the outputs of the registers 12, 14 and 16 for energizing current driving circuitry (not shown) for reading and writing into the cores (not shown). All reading and writing is done a character at a time. It vshould be noted also that whenever a character is read out of the memory unit 42 (or the `butler unit 96), gating and register circuits (not shown) restore that character into the same storage location to thereby provide a non-destructive type read-out storage unit. The memory unit 42 also has three read and write control circuits connected to the output circuit of the gating circuits 40 ofthe signal generator 36. These three lines will be referred to as the read command register line 90, the read memory address register line 91 and the write memory address register line 92. Whenever a high potential signal is developed on the read command register line 90, the character stored in the memory location specified by the states of the command address register l2 and the command character register 14 is read out. Similarly, whenever a high potential signal is developed on the read memory address register line 91, the character stored in the memory location specified by the memory address register 16 is read out.

A C register 94 is connected to the output circuit of the memory unit 42. The C register circuit 94 has flipfl-op circuits designated Cl through C4 which have double ended input circuits connected to the memory unit 42. The output signals of the memory unit 42 are always automatically stored into the C register 94 flip-flops independent of clock pulses. Thus, whenever a read signal is developed on either of the read lines or 91 the resultant output signals from the addressed memory location of the memory unit 42 are automatically read and stored by the C register 94. Outputs of the C register 94 tlip-ops are also connected to the memory unit 42 so that whenever a high potential signal is developed on the write memory address register line 92, the memory unit 42 automatically writes the character sto-red in the C register 94 into the memory location addressed by the memory address register 16.

The storage means 10 also has a buffer unit 96 which is a coincident current core unit similar to the memory unit 42, but smaller. The buffer unit 96 has individually addressable storage locations for storing characters of information. Connections are provided between the niemory unit 42 and the buffer unit 96 for transferring characters of information from the buffer unit 96 to the memory unit 42 (by control circuitry not shown).

The buffer unit 96 has a storage location 97 for storing the address of the next storage location in the butler unit 96 into which information is to be stored. The `butler unit 96 also has gating and current driving circuits (not shown) its core units (not shown), which are connected to the output circuit of the memory address register 16, for receiving address signals. The gating and driving circuits of the butler unit 96 are connected to a write control liuc 98 and a read butler address line Itltt. The lines 98 and 100 receive their control signals from the gating circuits 40 of the signal generator 36. Other input and output circuits of thc butler unit 96 are connected to the C register 94. Whenever a high potential signal is developed on the read buffer address lino 10U, the next buffer address stored in the buffer storage location 97 in the butler unit 96 is shifted out and stored in the C register 94. If the M8 flip-flop in the memory address register 16 represents a digit 1 and a high potential signal is developed on the write line 98, the contents of the C register 94 will be written into the storage location 97 of the butler unit 96. If the flip-[lop circuit M8 represents a digit 0 and a high potential signal is developed on the write line 98, the contents of the C register 94 is written into the storage location ot' the butler unit 96 specified by the contents of the memory address register 16. By way of example, it is assumed that the buffer unit 96 only receives address signals for writing from the units section of the memory address register 16, in contrast to the memory unit 42 which receives address signals from the entire memory address register 16.

The clock pulse generator 38 is connected to the memory unit 42 and the butler unit 96 for applying clock pulses thereto. Referring to FIG. 10, timing generators (not shown) are lprovided in the memory unit 42 and the butler unit 96 for causing a read and write cycle to take place under the control of signals on the above mentioned control lines in between the occurrence ul" clock 

17. IN A STORED PROGRAM COMPUTER THE COMBINATION COMPRISING: (A) MEMORY MEANS FOR STORING AND READING OUT INFORMATION A CHARACTER AT A TIME AND ARRANGED FOR STORING AND READING OUT COMMANDS COMPOSED OF AT LEAST TWO ADDRESSES AND AT LEAST TWO FIELD LENGTH SIGNALS ASSOCIATED WITH THE TWO ADDRESSES, SAID MEMORY MEANS INCLUDING MEANS FOR REPEATEDLY READING OUT THE ADDRESSES OF A COMMAND, (B) MEANS FOR INDIVIDUALLY STORING AND SELECTIVELY MODIFYING IN A PREDETERMINED MANNER THE TWO FIELD LENGTH SIGNALS OF A COMMAND READ OUT OF THE MEMORY MEANS AND THEREBY FORM A PLURALITY OF DIFFERENT FIELD LENGTH SIGNALS FOR EACH COMMAND, AND (C) MEANS FOR COMBINING THE PLURALITY OF FIELD LENGTH SIGNALS WITH THE CORRESPONDING ADDRESSES REPEATEDLY READ OUT OF THE MEMORY MEANS AND FOR FORMING A PLURALITY OF DIFFERENT ADDRESSES OF CHARACTERS IN THE MEMORY MEANS. 